Hot Chips 2026: Fujitsu Details Its 144-Core Monaka CPU With the Last-Level Cache on a Separate 5nm Die

Fujitsu gave a detailed look at its 144-core Monaka server CPU at Hot Chips 2026 on August 24, confirming for the first time that the Arm chip runs dual 256-bit SVE2 vector units, down from the 512-bit SVE in its A64FX predecessor, and that its entire last-level cache sits on a separate 5nm die beneath the 2nm compute die.

A three-die stack

Ryohei Okazaki, lead architect of Fujitsu’s processor development team, described the chip as “a made-in-Japan CPU, specifically engineered for AI performance and power efficiency,” built for what the company calls green AI data centers and subsidized by Japan’s New Energy and Industrial Technology Development Organization (NEDO). The chip splits into three tiers of silicon: a 2nm core die on TSMC N2P, a 5nm SRAM die on TSMC N5 that holds the whole last-level cache, and a 5nm IO die.

The core die stacks face-to-face on top of the SRAM die through hybrid bonding, sitting on the cooling side because it runs hottest, while the IO die connects to the SRAM die across a silicon interposer. Fujitsu keeps 2nm silicon under 30% of total die area, pushing everything that shrinks poorly onto the 5nm SRAM and IO dies to accelerate time to market for its 2nm chip.

Putting the full last-level cache on a distinct stacked die separates Monaka from AMD’s 3D V-Cache, which bonds extra SRAM on top of a compute die that already carries its own L3, and lines it up closer to Intel’s Clearwater Forest. The low-dropout voltage regulators also moved onto the 5nm SRAM die, placed directly beneath the core’s floating-point units to feed per-core dynamic voltage and frequency scaling.

Narrower vectors and AI inference support

Monaka drops the 512-bit SVE datapath of A64FX in favor of 256-bit SVE2, running two 256-bit vector units per core, each aligned to a 256-bit load/store unit, with FP8 and INT8 matrix support added for inference. It also drops HBM for 12-channel DDR5 at 8000 MT/s. The core carries mainframe-class reliability features, including ECC or duplication on the L1 and L2 caches, parity checks on execution units and registers, and a hardware instruction-retry mechanism.

Two SKUs are planned: a 350W air-cooled part at 2.1 GHz base and a 500W liquid-cooled part at 2.9 GHz base. Evaluation samples are available now, with volume production in 2027. Fujitsu estimates the 350W SKU at 4,355 GFLOPS in DGEMM and 69.7 TOPS in INT8, and the 500W SKU at 6,013 GFLOPS and 96.2 TOPS, with both rated around 500 GB/s in STREAM Triad. The company claims up to two times AI performance and over 50% TCO reduction against unnamed comparisons; these figures remain estimates until independent testing at the 2027 launch.

Positioning and what comes next

By 2027, Monaka’s 144 cores will land in the middle of the Arm server field rather than at the top of it, next to AWS Graviton5 (192 cores), Ampere AmpereOne (512 cores) and Microsoft’s Cobalt 200 (132 cores). NEDO subsidizes Monaka under a green data center program targeting 40% energy savings by 2030; its 2nm and 5nm dies come from TSMC rather than a domestic fab, a gap between the made-in-Japan design and Taiwanese manufacturing that Fujitsu and RIKEN have not yet closed. Monaka’s successor is already assigned to RIKEN’s FugakuNEXT flagship supercomputer, expected to operate around 2030.

Source: Tom’s Hardware

Cover image generated by AI for illustrative purposes only.